Prijava
Traži
Pregledavate arhivu oglasa objavljenih na www.posao.hr.
Ovaj oglas je istekao 10.03.2017. i više nije aktivan.
Sadržaj oglasa prikazan je isključivo u informativne svrhe.
Trenutno aktivne oglase pogledajte na www.posao.hr.
Ovaj oglas je istekao 10.03.2017. i više nije aktivan.
Sadržaj oglasa prikazan je isključivo u informativne svrhe.
Trenutno aktivne oglase pogledajte na www.posao.hr.
Layout engineer (m/f)
Oglas je istekao
Poslodavac:
Kategorija:
Mjesto rada:
Prague, Czech Republic
Rok prijave:
10.03.2017.
Plaća:
od 1 062 € do 1 593 € neto (Kalkulator plaće)
O poslu
Opis radnog mjesta:
The offered position is in the field of integrated circuit layout
• translation of schematic design into full custom layout in compliance with design rules
• verifications of layout to ensure all design requirements are met
• performing of floor planning for optimal die area
• generation of wire bonding diagram for assembly approval before the tap-out
• documentation and archival of database for future references after the tape-out.
• translation of schematic design into full custom layout in compliance with design rules
• verifications of layout to ensure all design requirements are met
• performing of floor planning for optimal die area
• generation of wire bonding diagram for assembly approval before the tap-out
• documentation and archival of database for future references after the tape-out.
Posebne pogodnosti:
• Attractive salary and wide range of corporate benefits
• Great opportunity to learn new things
• Good team spirit and friendly working environment
• Office located in Prague city center
• Relocation package
• Great opportunity to learn new things
• Good team spirit and friendly working environment
• Office located in Prague city center
• Relocation package
Vrsta posla:
stalni radni odnos
Županija:
Država:
Czech Republic
O zaposleniku
Znanja i kvalifikacije:
• Diploma in Electrical Engineering (with Microelectronics equivalent)
• Good knowledge of CMOS/BiCMOS process to support the Design Engineers to translate the schematic into mask layout
• Ability to generate full custom layout using Cadence Virtuoso Layout Editor
• Ability to perform layout verifications (DRC, ERC, LVS and XOR) using Mentor Graphics Calibre
• Basic knowledge of Linux/UNIX operating system
• For junior positions the candidate can be fresh graduate
• For senior positions, minimum of 5 years of related working experience is required; the candidate must be excellent in IC Layout knowledge with the capability to co-ordinate and supervise the project till completion with good quality for the tape-out
Contact e-mail: [email protected]
• Good knowledge of CMOS/BiCMOS process to support the Design Engineers to translate the schematic into mask layout
• Ability to generate full custom layout using Cadence Virtuoso Layout Editor
• Ability to perform layout verifications (DRC, ERC, LVS and XOR) using Mentor Graphics Calibre
• Basic knowledge of Linux/UNIX operating system
• For junior positions the candidate can be fresh graduate
• For senior positions, minimum of 5 years of related working experience is required; the candidate must be excellent in IC Layout knowledge with the capability to co-ordinate and supervise the project till completion with good quality for the tape-out
Contact e-mail: [email protected]
Minimalna stručna sprema:
Fakultet
Strani jezik:
engleski
Poznavanje rada na računalu:
napredno
